#Dsp builder altera code
Simulation and code generation from the model have been tested with the following versions of the software:
#Dsp builder altera software
Required Software The models described in this paper are from the example included with HDL Coder, Using Altera DSP Builder Advanced Blockset with HDL Coder. Some projects benefit from implementing a workflow that combines the native Simulink workflow, device-independent code, and code readability offered by HDL Coder, with Altera-specific features and optimizations offered by DSP Builder Advanced Blockset.1 This paper describes a new workflow for designs that are created with blocks from both Simulink and DSP Builder Advanced Blockset.2 Prior experience with MATLAB, Simulink, and DSP Builder will help you make the most of the examples in this paper. DSP Builder includes the DSP Builder Advanced Blockset, a high-level synthesis technology that optimizes the high-level, untimed netlists into low-level, pipelined hardware for the target Altera FPGA device and desired clock rate. Alternatively, engineers who specifically target Altera FPGAs can use DSP Builder, a plug-in to Simulink code generation software, to generate synthesizable hardware description language (HDL) code mapped to pre-optimized Altera implementations. Engineers who use Model-Based Design to target FPGAs or ASICs can design and simulate systems with MATLAB, Simulink, and Stateflow® and then generate bit-true, cycle-accurate, synthesizable Verilog® and VHDL® code using HDL Coder.
Introduction MATLAB® and Simulink for Model-Based Design provide signal, image, and video processing engineers with a development platform that spans design, modeling, simulation, code generation, and implementation.
This capability allows designers to reuse existing DSP Builder models when using HDL Coder to create new designs, or to incorporate target-optimized Altera IP blocks created for use with HDL Coder within Simulink models. We use an example to show how designers can integrate models built with DSP Builder Advanced Blockset into a Simulink® model, and how HDL Coder can generate HDL code for the complete design. Summary This document describes how HDL Coder™ from MathWorks can be used with Altera® DSP Builder in an integrated FPGA workflow. Model-Based Design for Altera FPGAs Using Simulink, HDL Coder, and Altera DSP Builder Advanced Blockset Model-Based Design for Altera FPGAs Using Simulink, HDL Coder, and Altera DSP Builder Advanced Blockset By Kiran Kintali and Yongfeng Gu